The present invention relates to a semiconductor memory device of dynamic-sensing type such as a dynamic RAM. More particularly, it relates to an improved semiconductor memory device comprising a word-line-resetting-ability regulating transistor.
With the recent development of electric appliances which have been reduced in size as well as in power consumption, lower-power dynamic RAMs have been in increasing demand. In the field of portable information appliances, there have been particularly great demands on low-power dynamic RAMs in which not only a current flowing during operation but also a current flowing during battery backup are reduced, since the commercial values of the information appliances depend on the duration of their continuous operation with a battery. In such a low-power dynamic RAM, circuitry has been designed to suppress an increase in current flowing during standby (standby current) during which the dynamic RAM is out of operation. The standby current is defined as a constantly flowing current resulting from a short circuit incessantly caused between a word line and a bit line by dust or the like, which has been accidentally included in the dynamic RAM in the fabrication process thereof.
As an example of the conventional semiconductor memory device (dynamic RAM) in which an increase in standby current has been suppressed, there has been known one disclosed in Japanese Laid-Open Patent Publication No. 3-88195.
FIG. 9(a) shows a principal portion of the dynamic RAM. FIG. 10 shows a chip on which a short circuit has been caused between a bit line and a word line by dust or the like, which has been accidentally included in the dynamic RAM in the fabrication process thereof.
In FIGS. 9(a) and 10 are shown: a memory cell MC; a pair of bit lines BL and/BL; and a word line WL. When the potential of the word line WL is high, the charges in the memory cell MC are released onto the bit line BL. In the drawings are also shown: a precharging transistor 50 for supplying & precharged potential to the above bit lines BL and/BL; a sense amplifier 51 for amplifying a potential difference (data) between the pair of bit lines BL and/BL; a column switch 52; data lines 53 along which the data on the pair of bit lines BL and/BL that has been amplified by the above sense amplifier 51 is transmitted via the above column switch 52.
The potential of the above word line WL is controlled to be at a set high value .phi.wn (which is Vpp level logic) by a word-line driver T8. while it is controlled to be at a ground value by a word-line-resetting- ability regulating transistor T10'. The above two transistors T8 and T10' are controlled by a row decoder 54, as shown in FIG. 9(a). The row decoder 54 consists of transistors T1 to T7, T30, and T31. The row decoder 54 controls a gate voltage VGLEAK of the word-line-resetting-ability regulating transistor T10' to be at two different values, one during operation and the other during standby. Specifically, as shown in FIG. 9(b), the gate voltage VGLEAK of the word-line-resetting-ability regulating transistor T10' is controlled to be at a value VPP during operation during which the transistor T30 is ON and to be at a set value VTT during standby during which the transistor T30 is OFF. The above voltage VPP corresponds to a power-source voltage for driving the row decoder 54. The above set voltage VTT is lower than the above power-source voltage VPP.
A description will be given to the operation of the above conventional embodiment in which, even when an access is made to a faulty address at which a short circuit has occurred between a bit line and a word line, a redundant circuit replaces a defective block containing the faulty address with a redundant block such that correct data in the redundant block is accessed.
During standby, all the bit lines BL and/BL are precharged to a bit-line precharged potential via the precharging transistor 50 in preparation for the subsequent operation. 0n the other hand, the word line WL is at the ground potential via the word-line-resetting-ability regulating transistor T10' so as to cut off a transfer gate between the bit line BL and the memory cell MC. In this state with no voltage application, if a short circuit has been caused between a bit line and a word line by the particle of dust R shown in the drawing, the precharged potential is allowed to flow as a standby current from the bit-line precharging transistor 50 to the ground by sequentially passing through the precharged bit line BL, dust R, word line WL, and word-line-resetting-ability regulating transistor T10'. In this path, since the gate voltage VGLEAK of the word-line-resetting-ability regulating transistor 10' is at the set low value VTT (e.g., on the order of 1 V slightly higher than the threshold voltage of the transistor T10'), the word-line-resetting-ability regulating transistor T10' is brought into a high-impedance state, so that the above standby current is limited to a sufficiently small value of about 10 .mu.A or less. In the case of not limiting the gate voltage VGLEAK to the low value VTT, the magnitude of the standby current becomes several hundreds of .mu.A, so that an increase in standby current resulting from a short circuit between a bit line and a word line is effectively suppressed by the word-line-resetting-ability regulating transistor T10' in the high-impedance state.
However, although the standby current resulting from a short circuit can be limited to a small value in the above conventional semiconductor memory device, the present inventors have found that an operating current having a large value flows disadvantageously during operation in the above conventional semiconductor memory device.
Specifically, as described above, the gate voltage VGLEAK of the word-line-resetting-ability regulating transistor T10' receives a chip activate signal (/RAS signal in a dynamic RAM) during operation and shifts to the logical High level of the row decoder circuit (the power-source voltage Vcc or an internal increased power-source voltage Vpp which ensures operation with a low voltage), thereby enhancing the word-line resetting ability of the word-line-resetting-ability regulating transistor T10'. Here, by way of example, a consideration will be given to a 16-Mbit general-purpose dynamic RAM (4 bits.times.4 megawords, 2048 refresh cycles). In this case, the number of actual word lines is 8192 to each one of which the above word-line-resetting-ability regulating transistor T10' is connected. The number of the word-line-resetting-ability regulating transistors T10' differs depending on the structure of the semiconductor integrated circuit. However, since the row decoder is normally disposed at the center of the chip, the number of the word-line-resetting-ability regulating transistors T10' becomes double the number of the word lines. If it is assumed that the word-line-resetting-ability regulating transistor T10' has a channel width of 2 .mu.m and a channel length of 1 .mu.m, the capacitance thereof will reaches 70 pF if calculated on the assumption that the gate oxide film is 14 nm thick. If the current flowing from the short-circuited portion is to be limited to about 10 .mu.A or lower in the word-line-resetting-ability regulating transistor T10' of this size, it is necessary to reduce the gate voltage VGLEAK to about 10 .mu.A or lower, as described above. On the foregoing assumption, if the cycle time during operation is 90 ns and Vpp level is 5 V, the on-chip current from the power source (which does not ensure operation with a low voltage) is calculated to reach 3 mA, since the word-line resetting ability of the word-line-resetting-ability regulating transistor T10' becomes higher than that during standby.
In the case of ensuring operation with a low voltage (e.g., 3.3 V), an internal increased-voltage power source is used as the power source for the above row decoder. The internal increased-voltage power source can be obtained by raising the power-source voltage to the increased voltage Vpp, which is high in potential (e.g., about 5 V), by means of an on-chip charge pump. However, since the efficiency with which the internal increased power-source voltage Vpp is generated is generally as low as about 50%, a power-source current flowing during operation reaches a higher value of about 6 mA.
Thus, in the conventional semiconductor memory device, although the standby current can be limited to the order of 10 .mu.A or lower even when there is an on-chip short circuit between a bit line and a word line, the power-source current during operation is considerably increased to the order of 3 mA or 6 mA, depending on the circuit structure. As a result, with portable appliances using a battery as a power source, the duration of their continuous operation is disadvantageously reduced.
Another problem of the conventional semiconductor memory device lies in a generating circuit of the voltage VGLEAK (equal to the low voltage VTT) applied to the gate of the word-line-resetting-ability regulating transistor T10' during standby.
Specifically, the above low-voltage generating circuit is composed of, e.g., a P-channel transistor and a diode-connected N-channel transistor, which have been connected in series between an external power source and the ground, so that a low voltage of about 1 V can be obtained from an intermediate node of the series circuit. However, since a through current flowing through the series circuit is increased if the above P-channel transistor is composed of a transistor having a low impedance, the P-channel transistor should be composed of a transistor having a high impedance, thereby reducing the above through current flowing through the series circuit to several .mu.A or lower. However, if the low-voltage generating circuit of this structure is used, a battery back-up current (such as a slow refresh current or a self-refresh current) for holding data with a battery cannot be suppressed effectively.
The above problem will be described more specifically. Although slow refreshing and self-refreshing are slightly different from each other in their cycles and operating manners, they refer to basically the same mode with intermittent operating states, in which a standby state lasting for 30 to several 100 .mu.s is followed by a single refreshing operation and then the standby state lasting for 30 to several 100 .mu.s takes place again, thereby holding data with low power. If it is assumed that the above low-voltage generating circuit is a simple series circuit composed of the P-channel transistor having a high impedance and an N-channel MOS transistor having been diode-connected to the ground, the output terminal of tile low-voltage generating circuit is connected to the gate of the word-line-resetting-ability regulating transistor, as described above. so that the voltage of the gate requires a long period of time on the order of several tens of .mu.s to lower from the potential level of the power source for the row decoder to the potential level of the low voltage VTT (about 1 V) immediately after the completion of the chip activate signal. Consequently, a comparatively large number of periods during which the gate potential of the word-line-resettlng-ability regulating transistor is higher than the low-voltage level of VTT are observed in the intermittent mode such as the slow refreshing mode or the self-refreshing mode. As a result, the state in which the word-line-resetting-ability regulating transistor has a low impedance lasts for a comparatively long period of time and hence the standby current resulting from a short circuit between a bit line and a word line is not effectively suppressed, so that a large amount of battery back-up current (slow refresh current or self-refresh current) is disadvantageously consumed.